Module state

CPU state representation, efficient representations of modifications to CPU state, and CPU state randomization.

Modules

• jit
  Efficient just-in-time generation of CPU states.
• random
  Random state generation.

Structs

• Addr
  Represents a 64-bit memory address.
• Area
  Represents an arbitrary memory area between two Addrs.
• MemoryState
  Memory state of a CPU.
• MemoryStateItemMut
  A mutable reference to a memory mapping in MemoryState.
• Page
  Represents a memory page.
• SplitDests
  Splits dests into smaller, non-overlapping chunks.
• StateByte
  A byte in a CPU state. Used in the SystemStateByteView to reference specific bytes in the system state.
• SystemState
  A CPU state consisting of the architecture-specific state part and memory mappings.
• SystemStateByteView
  A bytewise view of a system state. Allows the state to be read and written as if it were a contiguous block of bytes.
• SystemStateIoPair
  An input-output pair of SystemStates.

Enums

• Location
  A storage location in a CPU state.
• LocationKind
  The kind of a storage location.
• Permissions
  The access permissions of a memory mapping.
• SystemStateByteViewReg
  A register in the SystemStateByteView.

Constants

• MAX_MEMORY_SIZE
  The maximum number of bytes that a single memory mapping can be.

Traits

• AsSystemState
  NOTE: This value will be copied around a few times. Make sure it’s small enough!

Type Aliases

• MemoryEntry
  A memory mapping in a MemoryState.