Trait Arch

pub trait Arch:
    Copy
    + Clone
    + Debug
    + PartialEq
    + Eq
    + Hash
    + Default
    + PartialOrd
    + Ord
    + Send
    + Sync
    + 'static
where
    Self: Sized,
{
    type CpuState: CpuState<Self> + Clone + PartialEq + Eq + Send + Sync + Debug + Display;
    type Reg: Register + Copy + Clone + Debug + Display + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync;
    type GpReg: Register + NumberedRegister + Clone + Debug + Display + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync;
    type Flag: Flag + Clone + Debug + Display + PartialEq + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync;

    const PAGE_BITS: usize;
    const PC: Self::GpReg;
    const ZERO: Self::GpReg;
    const INSTRUCTION_ALIGNMENT: usize = 1usize;

    // Required methods
    fn reg(reg: Self::GpReg) -> Self::Reg;
    fn try_reg_to_gpreg(reg: Self::Reg) -> Option<Self::GpReg>;
    fn flagreg_to_flags(
        reg: Self::Reg,
        start_byte: usize,
        end_byte: usize,
    ) -> &'static [Self::Flag];
    fn iter_gpregs() -> impl Iterator<Item = Self::GpReg>;
    fn iter_regs() -> impl Iterator<Item = Self::Reg>;
}

Represents a CPU architecture.

Required Associated Constants

const PAGE_BITS: usize

The number of bits that are used in a page. The page size is 2**PAGE_BITS. For example, for a page size of 4096 bytes PAGE_BITS would be 12.

const PC: Self::GpReg

The program counter register.

const ZERO: Self::GpReg

The zero register. If the architecture does not explicitly list a zero register, you can invent one.

Provided Associated Constants

const INSTRUCTION_ALIGNMENT: usize = 1usize

The alignment of the instructions. Must be a multiple of 2.

Required Associated Types

type CpuState: CpuState<Self> + Clone + PartialEq + Eq + Send + Sync + Debug + Display

The CPU state representation.

type Reg: Register + Copy + Clone + Debug + Display + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync

The register representation.

type GpReg: Register + NumberedRegister + Clone + Debug + Display + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync

The general-purpose register representation. This should be equal to Self::Reg, or be a subset. General-purpose registers must be integers (see crate::value::ValueType).

These are the only registers that are used in address computations.

type Flag: Flag + Clone + Debug + Display + PartialEq + Eq + Hash + PartialOrd + Ord + Serialize + DeserializeOwned + Send + Sync

The flag representation.

A flag should always be part of a flag register.

See also Arch::flagreg_to_flags.

Required Methods

fn reg(reg: Self::GpReg) -> Self::Reg

Converts a general-purpose register into a generic register. This must always succeed.

fn try_reg_to_gpreg(reg: Self::Reg) -> Option<Self::GpReg>

Converts a generic register into a general-purpose register. If the generic register is not a general-purpose register, None is returned.

fn flagreg_to_flags( reg: Self::Reg, start_byte: usize, end_byte: usize, ) -> &'static [Self::Flag]

Returns the flags associated with the byte range in the flags register. By convention, a flag register should contain one flag per byte.

fn iter_gpregs() -> impl Iterator<Item = Self::GpReg>

Returns an iterator that iterates over all general-purpose registers. The zero register must not be included, as it is not a real register.

fn iter_regs() -> impl Iterator<Item = Self::Reg>

Returns an iterator that iterates over all registers. The zero register must not be included, as it is not a real register.

Dyn Compatibility

This trait is not dyn compatible.

In older versions of Rust, dyn compatibility was called "object safety", so this trait is not object safe.

Implementors

impl Arch for FakeArch

const PAGE_BITS: usize = 12usize

const PC: Self::GpReg = {transmute(0x00): <arch::fake::FakeArch as arch::Arch>::GpReg}

const ZERO: Self::GpReg = {transmute(0x14): <arch::fake::FakeArch as arch::Arch>::GpReg}

const INSTRUCTION_ALIGNMENT: usize = 1usize

type CpuState = FakeState

type Reg = FakeReg

type GpReg = FakeReg

type Flag = FakeFlag

impl Arch for X64Arch

const PAGE_BITS: usize = 12usize

const PC: Self::GpReg = {transmute(0x05): <arch::x64::X64Arch as arch::Arch>::GpReg}

const ZERO: Self::GpReg = {transmute(0x14): <arch::x64::X64Arch as arch::Arch>::GpReg}

const INSTRUCTION_ALIGNMENT: usize = 1usize

type CpuState = X64State

type Reg = X64Reg

type GpReg = GpReg

type Flag = X64Flag